Semiconductor random-access memories are widely used in electronic computing applications. For many applications, dynamic random access memory (DRAM) devices are preferred for such features as high storage density and low cost.
FIG. 1 shows a circuit diagram of a one-transistor DRAM cell. The cell includes a cell capacitor C that stores a charge corresponding to a data value. Cell capacitor C is coupled to a bitline BL through a field-effect transistor (FET) M1, and the gate of FET M1 is connected to a wordline WL.
Before the cell is read, the inherent capacitance CBL of bitline BL is precharged to a predetermined level. To retrieve the data value stored in cell capacitor C, wordline WL is pulled high to activate FET M1. This action causes charge sharing between cell capacitor C and inherent capacitance CBL. This charge sharing causes the voltage on bitline BL to vary from the precharge level according to the charge stored in cell capacitor C. A sense amplifier (not shown) detects and amplifies the voltage change on bitline BL to retrieve and output the corresponding data value.
One disadvantage of a DRAM cell as shown in FIG. 1 is that the level of the charge stored by cell capacitor C deteriorates over time (e.g. through leakage due to a nonideal dielectric). Once the charge level has deteriorated to the point where the sense amplifier can no longer properly detect the corresponding voltage change on bitline BL, the stored data value is lost. Therefore, it is necessary to refresh the charge stored in the cell capacitor from time to time.
When a DRAM cell is being refreshed, the stored data value cannot be accessed and a new data value cannot be stored. Therefore, the need for refresh activity imposes a limit on the performance of a memory system that includes DRAM devices. It is desirable to increase the period between refresh operations (the “refresh period”) in order to reduce the impact of this activity on memory system performance.
Increasing the refresh period may also reduce power consumption. In order to retain the information stored in its DRAM devices, for example, an electronic unit performs refresh operations even when the unit is not in active use. In the case of a handheld unit such as a cellular telephone, a personal digital assistant, or a notebook computer, power expended in performing DRAM refresh may represent a significant portion of the unit's total standby power drain. By reducing the number of refresh operations that are performed over a given period of time, increasing the refresh period may reduce the standby power consumption of the unit and help to extend the period over which such a unit may remain in standby mode for a single battery charge.
One technique for achieving a longer period between refresh operations is to increase the capacitance of cell capacitor C. However, this technique may include increasing the size of cell capacitor C, and undesirable effects of such an increase may include a reduction in storage density and/or a greatly increased circuit area.
Another technique for achieving a longer period between refresh operations is to reduce the ratio of the capacitance of the bitline to the capacitance of the cell capacitor. By increasing the magnitude of the voltage change on the bitline upon charge sharing, this technique may extend the period over which the charge on the cell capacitor remains detectable. Unfortunately, this technique may also include increasing the size of the cell capacitor. It is desirable to increase the period between refresh operations in a DRAM device without increasing the size of a cell capacitor.